PIC18F4620-I/ML【PDF 179/286 页】IC MCU FLASH 32KX16 44QFN

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Sheet目录3818

175页 176页 177页 178页 [179页]180页 181页 182页 183页

PIC18C601/801

DS39541A-page 290

Advance Information

2001 Microchip Technology Inc.

TABLE 22-19: MASTER SSP I2C BUS DATA REQUIREMENTS

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

THIGH

Clock high time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

101

TLOW

Clock low time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

102

SDA and SCL

rise time

100 kHz mode

—

1000

Cb is specified to be

from 10 to 400 pF

400 kHz mode

20 + 0.1Cb

300

1 MHz mode(1)

—

300

103

SDA and SCL

fall time

100 kHz mode

—

300

Cb is specified to be

from 10 to 400 pF

400 kHz mode

20 + 0.1Cb

300

1 MHz mode(1)

—

100

TSU:STA

START condition

setup time

100 kHz mode

2(TOSC)(BRG + 1)

—

Only relevant for

Repeated START

condition

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

THD:STA

START condition

hold time

100 kHz mode

2(TOSC)(BRG + 1)

—

After this period, the first

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

106

THD:DAT

Data input

hold time

100 kHz mode

—

400 kHz mode

0.9

1 MHz mode(1)

TBD

—

107

TSU:DAT

Data input

setup time

100 kHz mode

250

—

(Note 2)

400 kHz mode

100

—

1 MHz mode(1)

TBD

—

TSU:STO

STOP condition

setup time

100 kHz mode

2(TOSC)(BRG + 1)

—

400 kHz mode

2(TOSC)(BRG + 1)

—

1 MHz mode(1)

2(TOSC)(BRG + 1)

—

109

TAA

Output valid from

clock

100 kHz mode

—

3500

400 kHz mode

—

1000

1 MHz mode(1)

——

110

TBUF

Bus free time

100 kHz mode

4.7

—

Time the bus must be

free before a new

transmission can start

400 kHz mode

1.3

—

1 MHz mode(1)

TBD

—

D102

Bus capacitive loading

—

400

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107

≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line. Before the SCL line is released, parameter #102 + parameter

#107 = 1000 + 250 = 1250 ns (for 100 kHz mode).

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